1. Technical Field
This invention relates to a trenched power semiconductor device and a fabrication method thereof, and more particularly relates to a closed-cell trenched power semiconductor device and a fabrication method thereof.
2. Description of Related Art
The cell layout of the trenched power semiconductor devices can be sorted as closed cell and the striped cell. A major difference between the two types lies in the arrangement of the trenched gates. For the striped-cell trenched semiconductor device, the trenched gates are stripe-shaped and arranged in the body layer with substantially identical pitch. For the closed-cell trenched semiconductor device, the trenched gates are arranged as a network in the body layer and define a plurality of square areas on the body layer. In contrast with the striped-cell trenched semiconductor device, the closed-cell one with a greater channel width per unit area has the advantage of low on resistance.
FIG. 1 is a top view of a typical closed-cell trenched power semiconductor device. As shown, the trenched gate of the closed-cell trenched power semiconductor device is arranged in the body layer in array and defines a plurality of square areas 10, which is regarded as the unit cell. The source region 101 is located in the square areas 10, which adjacent to the trenched gate 102. In the middle of the square area 10 has a heavily doped region 103 acting as a conducting route between the body layer and the source metal layer.
FIG. 1A is a schematic view showing the real dimension of the unit cell of the closed-cell trenched power semiconductor device in FIG. 1. The unit of the dimension labeled in the figure is micron. The channel width Cw per unit area of the closed-cell power semiconductor device may be calculated by the function (1):(L11*4)/(L12*L12)=Cw  (1)
According to the above function (1), the value of Cw equals 2.4 micron when the length of L11 is 0.6 micron, and the length of L12 is 1 micron. As the line width shrinks, the value of the channel width per unit area may be enhanced. Take the unit cell 10b in FIG. 1B as an example. The line width of the closed-cell trenched power semiconductor device is reduced to 75% of the original line width as shown in FIG. 1A. The value of channel width Cw per unit area may be calculated by the function (2):(L21*4)/(L22*L22)=Cw  (2)
According to the above function (2), when the length of L21 is 0.45 micron and the length of L22 is 0.75 micron, the value of Cw equals 3.2 micron. Although the shrinkage of cell dimension is helpful for enhancing channel width to reduce on resistance, it has a significant drawback that the distance between the heavily doped region 16,16′ at the middle of the square area and the surrounding gate structure 12,12′ is also reduced. (the width t1 of the FIG. 1A is reduced to the width t2 of the FIG. 1B.) The impurities in the heavily doped region 16′ may easily diffuse to the adjacent area of the gate structure 12′ such that the doping concentration of the channel would be varied so as to influence the predetermined threshold voltage of the power semiconductor device.